The invention relates to integrated circuits, and in particular to a clocking apparatus and method for a monolithic integrated circuit.
As the complexity, scope and signal processing speed of integrated circuits increase, their application increasingly entails the problem that the circuits also act as significant sources of electromagnetic interference. This problem involves not only the immediate environment or circuits not immediately adjacent, but also the actual circuit as an interference source affecting itself. This is especially true when analog stages are integrated into the system together with the purely digital signal-processing stages. These are often located in the input region in which analog signals must still be processed. Examples of analog stages include input amplifiers, analog-to-digital converters, or mixers. Interference is especially detrimental because the interference, or its harmonics, may enter the useful signal either directly or through its mixing products, as the signal amplitudes of the useful signal are still very small. Any superposition of additional interference signals may make itself evident immediately, thereby significantly disturbing the function of the overall circuit.
The main source of interference involves high current peaks that are directly coupled during synchronous signal processing to the system clock by which a great number of switching operations are triggered simultaneously. In circuits using complementary circuitry, such as CMOS, the gate capacities of the switching transistors are charged or discharged by the clock edges. Here the working edge of the system clock triggers all synchronous switching operations which are followed by a greater or lesser number of asynchronously occurring switching operations during this operating cycle. All switching operations must be completed before the new working edge of the system clock. Simultaneous with the charging and discharging of the gate capacitances, diffusion and line capacitances are also charged or discharged. All of the synchronously triggered charges and discharges are added to the internal and external clock lines and supply lines to form current peaks that generate electromagnetic and capacitive interference signals through the external supply lines as well as through the externally connected data lines.
The fundamental frequency of these interference signals is generally the clock frequency. Due to the great edge steepness of the current peaks, a corresponding number of strong harmonics are created as a result. In principle, the disadvantage of these simultaneously occurring switching operations may be avoided by using asynchronous sequential circuits. However, these add significantly more complexity to the development and layout of the circuit. In addition, few software tools exist that support an asynchronous design. Additional examples of known mechanisms for reducing internal and external interference include the following:
1. A favorable arrangement of the supply terminals which provide for simple external blocking by filtering such as capacitors or ferrite materials.
2. Internal blocking measures such as integrated blocking capacitors.
3. Internal and external shielding measures using grounding lines.
4. Automatically controlled output stages which prevent the rise and fall times of the switching edges from becoming too steep.
5. The lowest possible capacitive loads for charging and discharging.
6. Modulation of the clock frequency using a predetermined or random signal.
These measures are helpful in many cases, especially in relation to noncritical circuits. Their effectiveness is insufficient, however, for especially critical circuits.
Therefore, there is a need to reduce the effect of internal and external interference even in relatively complex monolithic integrated circuits.